Parallel Processing to Enhance Performance of ATPGs

Automatic Test Pattern Generation (ATPG) is known to be an NP hard problem. To solve such problems, heuristics are used that often require a huge amount of processing. Parallel processing has, thus, been applied to speed up the test generation. There are a few possible solutions to this problem. This report surveys the major techniques used to allow parallel generation of test vectors. We discuss fault parallelism, heuristic parallelism, search space parallelism, functional/algorithmic parallelism and the circuit parallelism. We discuss the pros and cons of these techniques and compare their performances. A few variants of these approaches are also discussed. We use fault partitioning in conjunction with FAN algorithm and report the achieved speedups for ISCAS-85 circuits.